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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-03-07 21:32:31 +0000
committerGitHub <noreply@github.com>2019-03-07 21:32:31 +0000
commit84781219c87c0b9148e318f3e358ef7de03e251c (patch)
tree5adffe477189c81f1759446ad9efc7ea46f68702 /bsp/coreip-e24-arty/design.dts
parent90ab2c8561eb532b382206c8bf3ec1af74f18257 (diff)
parent92d0f3e15ddfeb3d3a640d9bdd3471553e14ed7e (diff)
Merge pull request #196 from sifive/update-metal
Update Metal with GPIO and Cache APIs
Diffstat (limited to 'bsp/coreip-e24-arty/design.dts')
-rw-r--r--bsp/coreip-e24-arty/design.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/bsp/coreip-e24-arty/design.dts b/bsp/coreip-e24-arty/design.dts
index dd35d75..b636a82 100644
--- a/bsp/coreip-e24-arty/design.dts
+++ b/bsp/coreip-e24-arty/design.dts
@@ -7,7 +7,7 @@
model = "SiFive,FE240G";
chosen {
stdout-path = "/soc/serial@20000000:115200";
- mee,entry = <&L7 0x400000>;
+ metal,entry = <&L7 0x400000>;
};
L17: aliases {
serial0 = &L6;