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authorBunnaroath Sou <35707615+bsousi5@users.noreply.github.com>2019-02-01 13:55:58 -0800
committerGitHub <noreply@github.com>2019-02-01 13:55:58 -0800
commitd9a6c0abd5e98697aae8273342961895512890bf (patch)
tree62035b849ea878ea67eb239c2d94c3ed72462be0 /bsp/coreip-e24-arty/openocd.cfg
parentd730034120ff78f1cb06d49b6a2e7470b6f43993 (diff)
parent0fd5ac749341e8b7dd8f91134a1c572ac1cb5e9b (diff)
Merge pull request #168 from sifive/e24-arty
E24 arty support
Diffstat (limited to 'bsp/coreip-e24-arty/openocd.cfg')
-rw-r--r--bsp/coreip-e24-arty/openocd.cfg30
1 files changed, 30 insertions, 0 deletions
diff --git a/bsp/coreip-e24-arty/openocd.cfg b/bsp/coreip-e24-arty/openocd.cfg
new file mode 100644
index 0000000..34b9f88
--- /dev/null
+++ b/bsp/coreip-e24-arty/openocd.cfg
@@ -0,0 +1,30 @@
+adapter_khz 10000
+
+#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+interface ftdi
+ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi_vid_pid 0x15ba 0x002a
+
+ftdi_layout_init 0x0808 0x0a1b
+ftdi_layout_signal nSRST -oe 0x0200
+ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi_layout_signal LED -data 0x0800
+#
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank my_first_flash fespi 0x40000000 0 0 0 $_TARGETNAME 0x20004000
+init
+#reset
+if {[ info exists pulse_srst]} {
+ ftdi_set_signal nSRST 0
+ ftdi_set_signal nSRST z
+}
+halt
+#flash protect 0 64 last off