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authorBunnaroath Sou <bsou@sifive.com>2019-03-18 12:58:11 -0700
committerBunnaroath Sou <bsou@sifive.com>2019-03-18 12:58:11 -0700
commit0fe5ca97956cc15effd0c459a81c8caacbc80ac3 (patch)
treead49ff7afc82f2ae691b8ebea1f8f88ae806b14c /bsp/coreip-e24-arty
parent6695a994b01585ae3dce0e492de3c4e3feb2ae4f (diff)
Update Arty clock to reflects HW
Diffstat (limited to 'bsp/coreip-e24-arty')
-rw-r--r--bsp/coreip-e24-arty/design.dts2
-rw-r--r--bsp/coreip-e24-arty/metal.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/bsp/coreip-e24-arty/design.dts b/bsp/coreip-e24-arty/design.dts
index b636a82..9d08297 100644
--- a/bsp/coreip-e24-arty/design.dts
+++ b/bsp/coreip-e24-arty/design.dts
@@ -22,7 +22,7 @@
reg = <0x0>;
riscv,isa = "rv32imafc";
status = "okay";
- timebase-frequency = <1000000>;
+ timebase-frequency = <32000000>;
hardware-exec-breakpoint-count = <4>;
L3: interrupt-controller {
#interrupt-cells = <1>;
diff --git a/bsp/coreip-e24-arty/metal.h b/bsp/coreip-e24-arty/metal.h
index 129eeee..c9ccb86 100644
--- a/bsp/coreip-e24-arty/metal.h
+++ b/bsp/coreip-e24-arty/metal.h
@@ -150,7 +150,7 @@ struct __metal_driver_fixed_clock __metal_dt_clock_0 = {
struct __metal_driver_cpu __metal_dt_cpu_0 = {
.vtable = &__metal_driver_vtable_cpu,
.cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
- .timebase = 1000000UL,
+ .timebase = 32000000UL,
.interrupt_controller = &__metal_dt_interrupt_controller.controller,
};