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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-06-19 15:26:20 -0700 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-06-19 15:27:52 -0700 |
| commit | 0d6aad1a8c3b806716add4b5bb6954984d508ab3 (patch) | |
| tree | 9c6ef58cd92036a9c9eb23713e8f646af43e456e /bsp/coreip-e24-rtl/README.md | |
| parent | 00a58b4a52a6a3678c1359d76a8647fd5f528b9b (diff) | |
Delete coreip BSPs
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-e24-rtl/README.md')
| -rw-r--r-- | bsp/coreip-e24-rtl/README.md | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/bsp/coreip-e24-rtl/README.md b/bsp/coreip-e24-rtl/README.md deleted file mode 100644 index 1996262..0000000 --- a/bsp/coreip-e24-rtl/README.md +++ /dev/null @@ -1,8 +0,0 @@ -The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities by implementing the RISC-V ISA’s F standard extension. The E24’s efficiency, coupled with hardware floating-point capabilities, make it exceptional at motor control, sensor fusion, and IoT applications. - -This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - -- 1 hart with RV32IMAFC core -- 4 hardware breakpoints -- Physical Memory Protection with 4 regions - |