Merge pull request #254 from sifive/dts-pmpregions

Update to new-style riscv,pmpregions property

8 files changed, 21 insertions, 24 deletions

diff --git a/bsp/coreip-e24-rtl/design.dts b/bsp/coreip-e24-rtl/design.dts
index da1b792..a254a10 100644
--- a/bsp/coreip-e24-rtl/design.dts
+++ b/bsp/coreip-e24-rtl/design.dts
@@ -14,6 +14,7 @@
 			device_type = "cpu";
 			reg = <0x0>;
 			riscv,isa = "rv32imafc";
+			riscv,pmpregions = <4>;
 			status = "okay";
 			timebase-frequency = <1000000>;
                         hardware-exec-breakpoint-count = <4>;
@@ -29,10 +30,6 @@
 		#size-cells = <1>;
 		compatible = "SiFive,FE240G-soc", "fe240-soc", "sifive-soc", "simple-bus";
 		ranges;
- 		pmp: pmp@0 {
- 			compatible = "riscv,pmp";
- 			regions = <8>;
- 		};
 		L11: ahb-periph-port@20000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/bsp/coreip-e24-rtl/metal-inline.h b/bsp/coreip-e24-rtl/metal-inline.h
index dd34d93..460e9d3 100644
--- a/bsp/coreip-e24-rtl/metal-inline.h
+++ b/bsp/coreip-e24-rtl/metal-inline.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 21-05-2019 10-54-34        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
@@ -24,6 +24,7 @@
 /* --------------------- cpu ------------ */
 extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
 extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu);
 
 
 /* --------------------- sifive_plic0 ------------ */
@@ -131,11 +132,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
     .init_done = 0,
 };
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
-
 /* From interrupt_controller@2000000 */
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
     .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
diff --git a/bsp/coreip-e24-rtl/metal-platform.h b/bsp/coreip-e24-rtl/metal-platform.h
index dabc75f..7806168 100644
--- a/bsp/coreip-e24-rtl/metal-platform.h
+++ b/bsp/coreip-e24-rtl/metal-platform.h
@@ -1,17 +1,12 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 21-05-2019 10-54-34        */
 /* ----------------------------------- */
 
 #ifndef COREIP_E24_RTL__METAL_PLATFORM_H
 #define COREIP_E24_RTL__METAL_PLATFORM_H
 
-/* From pmp@0 */
-#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
-
-#define METAL_RISCV_PMP
-
 /* From interrupt_controller@2000000 */
 #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
 #define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL
diff --git a/bsp/coreip-e24-rtl/metal.default.lds b/bsp/coreip-e24-rtl/metal.default.lds
index d021e81..b1c05ca 100644
--- a/bsp/coreip-e24-rtl/metal.default.lds
+++ b/bsp/coreip-e24-rtl/metal.default.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 21-05-2019 10-54-34        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
diff --git a/bsp/coreip-e24-rtl/metal.h b/bsp/coreip-e24-rtl/metal.h
index 6d97dbd..bbe0508 100644
--- a/bsp/coreip-e24-rtl/metal.h
+++ b/bsp/coreip-e24-rtl/metal.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 21-05-2019 10-54-34        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
@@ -80,7 +80,7 @@ struct __metal_driver_cpu __metal_dt_cpu_0;
 
 struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
-struct metal_pmp __metal_dt_pmp_0;
+struct metal_pmp __metal_dt_pmp;
 
 /* From interrupt_controller@2000000 */
 struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000;
@@ -123,6 +123,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s
 	}
 }
 
+static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 4;
+	}
+	else {
+		return 0;
+	}
+}
+
 
 
 /* --------------------- sifive_plic0 ------------ */
@@ -694,8 +704,7 @@ asm (".weak __metal_cpu_table");
 struct __metal_driver_cpu *__metal_cpu_table[] = {
 					&__metal_dt_cpu_0};
 
-/* From pmp@0 */
-#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0)
+#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp)
 
 /* From interrupt_controller@2000000 */
 #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller)
diff --git a/bsp/coreip-e24-rtl/metal.ramrodata.lds b/bsp/coreip-e24-rtl/metal.ramrodata.lds
index 199cc1f..59bfadc 100644
--- a/bsp/coreip-e24-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-e24-rtl/metal.ramrodata.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 21-05-2019 10-54-34        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
diff --git a/bsp/coreip-e24-rtl/metal.scratchpad.lds b/bsp/coreip-e24-rtl/metal.scratchpad.lds
index 8bea50d..ccd53eb 100644
--- a/bsp/coreip-e24-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-e24-rtl/metal.scratchpad.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 21-05-2019 10-54-34        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
diff --git a/bsp/coreip-e24-rtl/settings.mk b/bsp/coreip-e24-rtl/settings.mk
index 4d6b13e..942bc62 100644
--- a/bsp/coreip-e24-rtl/settings.mk
+++ b/bsp/coreip-e24-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 21-05-2019 10-54-34        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imafc