diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-21 10:51:18 -0700 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-21 10:54:29 -0700 |
| commit | b87018b8a5afa98a6f799527d9a4417290349a4a (patch) | |
| tree | bfd29bb74aeade1c864ef431691b86e2ea0ab442 /bsp/coreip-e24-rtl | |
| parent | 1054095bdf4d5a989ed1267051cc6fd6eefc2fcd (diff) | |
Modify BSP DTSs to use riscv,pmpregions property
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-e24-rtl')
| -rw-r--r-- | bsp/coreip-e24-rtl/design.dts | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/bsp/coreip-e24-rtl/design.dts b/bsp/coreip-e24-rtl/design.dts index da1b792..a254a10 100644 --- a/bsp/coreip-e24-rtl/design.dts +++ b/bsp/coreip-e24-rtl/design.dts @@ -14,6 +14,7 @@ device_type = "cpu"; reg = <0x0>; riscv,isa = "rv32imafc"; + riscv,pmpregions = <4>; status = "okay"; timebase-frequency = <1000000>; hardware-exec-breakpoint-count = <4>; @@ -29,10 +30,6 @@ #size-cells = <1>; compatible = "SiFive,FE240G-soc", "fe240-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L11: ahb-periph-port@20000000 { #address-cells = <1>; #size-cells = <1>; |