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| author | Bunnaroath Sou <bsou@sifive.com> | 2019-03-01 15:28:49 -0800 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-03-01 15:28:49 -0800 |
| commit | 43b6767541e6b20d7f7c2aef39b3a4748e53b6e4 (patch) | |
| tree | c5dd195d26a51b2b55b91684374ab2815cdb8f4b /bsp/coreip-e24/README.md | |
| parent | fb3cddda6c0342ae6c91918e769eecafbabb55b0 (diff) | |
Update CoreIPs E20, E21, E31 and E24 for 19.2 rel
Diffstat (limited to 'bsp/coreip-e24/README.md')
| -rw-r--r-- | bsp/coreip-e24/README.md | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/bsp/coreip-e24/README.md b/bsp/coreip-e24/README.md new file mode 100644 index 0000000..1996262 --- /dev/null +++ b/bsp/coreip-e24/README.md @@ -0,0 +1,8 @@ +The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities by implementing the RISC-V ISA’s F standard extension. The E24’s efficiency, coupled with hardware floating-point capabilities, make it exceptional at motor control, sensor fusion, and IoT applications. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAFC core +- 4 hardware breakpoints +- Physical Memory Protection with 4 regions + |