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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-06-21 16:36:57 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-21 16:36:57 +0000 |
| commit | 0f5761d7d32edddf93f302f52b903e8acca08c5e (patch) | |
| tree | 46ff4106f51fb6d5f682cf6af73ef1a4ab5f147e /bsp/coreip-e31-arty/README.md | |
| parent | eecf71d7cf0ec12997dbceffde190b1086595908 (diff) | |
| parent | 713237cb963ebf81aca0715d8a770fdbe5d71cb9 (diff) | |
Merge pull request #287 from sifive/remove-coreip-bsps
Remove all CoreIP BSPs
Diffstat (limited to 'bsp/coreip-e31-arty/README.md')
| -rw-r--r-- | bsp/coreip-e31-arty/README.md | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/bsp/coreip-e31-arty/README.md b/bsp/coreip-e31-arty/README.md deleted file mode 100644 index c6558cb..0000000 --- a/bsp/coreip-e31-arty/README.md +++ /dev/null @@ -1,14 +0,0 @@ -The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. - -This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: - -- 1 hart with RV32IMAC core -- 4 hardware breakpoints -- Physical Memory Protection with 8 regions -- 16 local interrupts signal that can be connected to off core complex devices -- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels -- GPIO memory with 16 interrupt lines -- SPI memory with 1 interrupt line -- Serial port with 1 interrupt line -- 4 RGB LEDS -- 4 Buttons and 4 Switches |