summaryrefslogtreecommitdiff
path: root/bsp/coreip-e31-arty/design.dts
diff options
context:
space:
mode:
authorNathaniel Graff <nathaniel.graff@sifive.com>2019-01-30 19:37:59 +0000
committerGitHub <noreply@github.com>2019-01-30 19:37:59 +0000
commit89d973abd94faf74d7486a6c5e044935f5d63e9d (patch)
treec7188e2bfad20a2750a4155ff623a16541abfb74 /bsp/coreip-e31-arty/design.dts
parentb629a19514606cb5dd19e0cd433b60922343f6a8 (diff)
parentc615e937538d438c46efd46f9254a2a74b591205 (diff)
Merge pull request #157 from sifive/mee-pmp-no-vtable
Add PMP example
Diffstat (limited to 'bsp/coreip-e31-arty/design.dts')
-rw-r--r--bsp/coreip-e31-arty/design.dts4
1 files changed, 4 insertions, 0 deletions
diff --git a/bsp/coreip-e31-arty/design.dts b/bsp/coreip-e31-arty/design.dts
index 3e12f77..96698e9 100644
--- a/bsp/coreip-e31-arty/design.dts
+++ b/bsp/coreip-e31-arty/design.dts
@@ -45,6 +45,10 @@
compatible = "fixed-clock";
clock-frequency = <32500000>;
};
+ pmp: pmp@0 {
+ compatible = "riscv,pmp";
+ regions = <8>;
+ };
L1: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L3 3 &L3 7>;