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| author | Hsiang-Chia.Huang <hsiangchiah@sifive.com> | 2019-05-22 00:37:14 -0700 |
|---|---|---|
| committer | Hsiang-Chia.Huang <hsiangchiah@sifive.com> | 2019-05-22 19:58:17 -0700 |
| commit | 7817c5e85cb6f9f6d5b98f6702fa4b7d1fb99e02 (patch) | |
| tree | dc9652a6765fefad29d18da1a19645de104d8639 /bsp/coreip-e31-arty | |
| parent | 9946f2062837098088e4c9701614a2eeffaa921b (diff) | |
Setup default options for dhrystone release.
Diffstat (limited to 'bsp/coreip-e31-arty')
| -rw-r--r-- | bsp/coreip-e31-arty/settings.mk | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk index b9be584..3e8ebf8 100644 --- a/bsp/coreip-e31-arty/settings.mk +++ b/bsp/coreip-e31-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 22-05-2019 00-09-02 # # ----------------------------------- # RISCV_ARCH=rv32imac @@ -9,3 +9,4 @@ RISCV_ABI=ilp32 RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 |