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authorBunnaroath Sou <bsou@sifive.com>2019-02-25 18:57:35 -0800
committerBunnaroath Sou <bsou@sifive.com>2019-02-25 18:57:35 -0800
commite18401806b38ca0f60394780191df4b72cb2f88a (patch)
tree50c31a3efbe1f1acce3aeec706c0d8d1227c0964 /bsp/coreip-e31-arty
parentbbea559f684a5eee7df45429ed55d41330f44474 (diff)
Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty
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+The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications.
+
+This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports:
+ - 1 hart with RV32IMAC core
+ - 4 hardware breakpoints
+ - Physical Mempory Protectin with 8 regions
+ - 16 local interrupts signal that can be connected to off core complex devices
+ - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+ - GPIO memory with 16 interrupt lines
+ - SPI memory with 1 intterupt line
+ - Serial port with 1 interrupt line
+ - 4 RGB LEDS
+ - 4 Buttons and 4 Switches
+~