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| author | Bunnaroath Sou <35707615+bsousi5@users.noreply.github.com> | 2019-03-01 10:05:34 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-01 10:05:34 -0800 |
| commit | fb3cddda6c0342ae6c91918e769eecafbabb55b0 (patch) | |
| tree | ee323a74e2355cfedd0d528a407a6d5d252e8a7c /bsp/coreip-e31-arty | |
| parent | bbea559f684a5eee7df45429ed55d41330f44474 (diff) | |
| parent | cbda1f5070e04de7ed3770d5dfd2e4f9abfc84b0 (diff) | |
Merge pull request #183 from sifive/e-series
Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty
Diffstat (limited to 'bsp/coreip-e31-arty')
| -rw-r--r-- | bsp/coreip-e31-arty/README.md | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/bsp/coreip-e31-arty/README.md b/bsp/coreip-e31-arty/README.md new file mode 100644 index 0000000..c6558cb --- /dev/null +++ b/bsp/coreip-e31-arty/README.md @@ -0,0 +1,14 @@ +The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches |