diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-07 22:47:38 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-07 22:47:38 +0000 |
| commit | 2b9cbfe9011bca74aee3c1204d7db4b4236b23f0 (patch) | |
| tree | fccb6fa1d7c2c065642cb21cc4d421e3ae8206eb /bsp/coreip-e31-rtl/README.md | |
| parent | c6c0fbf23d1fc8aa9b99eae19b6e3741c8d51548 (diff) | |
| parent | 983a630b07f08af869adc78cb37bf634389519af (diff) | |
Merge pull request #197 from sifive/rename-rtl-targets
Rename coreip-X to coreip-X-rtl
Diffstat (limited to 'bsp/coreip-e31-rtl/README.md')
| -rw-r--r-- | bsp/coreip-e31-rtl/README.md | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/bsp/coreip-e31-rtl/README.md b/bsp/coreip-e31-rtl/README.md new file mode 100644 index 0000000..324369d --- /dev/null +++ b/bsp/coreip-e31-rtl/README.md @@ -0,0 +1,9 @@ +The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |