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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-03-07 22:47:38 +0000
committerGitHub <noreply@github.com>2019-03-07 22:47:38 +0000
commit2b9cbfe9011bca74aee3c1204d7db4b4236b23f0 (patch)
treefccb6fa1d7c2c065642cb21cc4d421e3ae8206eb /bsp/coreip-e31-rtl/README.md
parentc6c0fbf23d1fc8aa9b99eae19b6e3741c8d51548 (diff)
parent983a630b07f08af869adc78cb37bf634389519af (diff)
Merge pull request #197 from sifive/rename-rtl-targets
Rename coreip-X to coreip-X-rtl
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+The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications.
+
+This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports:
+
+- 1 hart with RV32IMAC core
+- 4 hardware breakpoints
+- Physical Memory Protection with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels