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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-05-23 14:16:04 -0700
committerNathaniel Graff <nathaniel.graff@sifive.com>2019-05-28 10:06:45 -0700
commit12485f45ebb7f96dc60951bf4365533652ac5139 (patch)
treeb38ce688ab045a41bbdcdc90462fb4e4646a0b5d /bsp/coreip-e31-rtl
parentf7960558fd35113a89025f0971f3779d884f9a53 (diff)
Update BSPs
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-e31-rtl')
-rw-r--r--bsp/coreip-e31-rtl/metal-inline.h2
-rw-r--r--bsp/coreip-e31-rtl/metal-platform.h2
-rw-r--r--bsp/coreip-e31-rtl/metal.default.lds3
-rw-r--r--bsp/coreip-e31-rtl/metal.h14
-rw-r--r--bsp/coreip-e31-rtl/metal.ramrodata.lds3
-rw-r--r--bsp/coreip-e31-rtl/metal.scratchpad.lds3
-rw-r--r--bsp/coreip-e31-rtl/settings.mk4
7 files changed, 18 insertions, 13 deletions
diff --git a/bsp/coreip-e31-rtl/metal-inline.h b/bsp/coreip-e31-rtl/metal-inline.h
index a5035c7..bce8f44 100644
--- a/bsp/coreip-e31-rtl/metal-inline.h
+++ b/bsp/coreip-e31-rtl/metal-inline.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-05-57 */
/* ----------------------------------- */
#ifndef ASSEMBLY
diff --git a/bsp/coreip-e31-rtl/metal-platform.h b/bsp/coreip-e31-rtl/metal-platform.h
index 9e03fae..f47c1ab 100644
--- a/bsp/coreip-e31-rtl/metal-platform.h
+++ b/bsp/coreip-e31-rtl/metal-platform.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-05-57 */
/* ----------------------------------- */
#ifndef COREIP_E31_RTL__METAL_PLATFORM_H
diff --git a/bsp/coreip-e31-rtl/metal.default.lds b/bsp/coreip-e31-rtl/metal.default.lds
index f687862..3771ba4 100644
--- a/bsp/coreip-e31-rtl/metal.default.lds
+++ b/bsp/coreip-e31-rtl/metal.default.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-05-57 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -30,6 +30,7 @@ SECTIONS
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
PROVIDE(__metal_boot_hart = 0);
+ PROVIDE(__metal_chicken_bit = 0);
.init :
diff --git a/bsp/coreip-e31-rtl/metal.h b/bsp/coreip-e31-rtl/metal.h
index 9e977af..0f72ce7 100644
--- a/bsp/coreip-e31-rtl/metal.h
+++ b/bsp/coreip-e31-rtl/metal.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-05-57 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -71,13 +71,13 @@
#include <metal/drivers/fixed-clock.h>
#include <metal/memory.h>
-#include <metal/drivers/riscv,clint0.h>
-#include <metal/drivers/riscv,cpu.h>
-#include <metal/drivers/riscv,plic0.h>
+#include <metal/drivers/riscv_clint0.h>
+#include <metal/drivers/riscv_cpu.h>
+#include <metal/drivers/riscv_plic0.h>
#include <metal/pmp.h>
-#include <metal/drivers/sifive,local-external-interrupts0.h>
-#include <metal/drivers/sifive,global-external-interrupts0.h>
-#include <metal/drivers/sifive,test0.h>
+#include <metal/drivers/sifive_local-external-interrupts0.h>
+#include <metal/drivers/sifive_global-external-interrupts0.h>
+#include <metal/drivers/sifive_test0.h>
struct metal_memory __metal_dt_mem_testram_20000000;
diff --git a/bsp/coreip-e31-rtl/metal.ramrodata.lds b/bsp/coreip-e31-rtl/metal.ramrodata.lds
index e75a025..d6811a2 100644
--- a/bsp/coreip-e31-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-e31-rtl/metal.ramrodata.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-05-57 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -30,6 +30,7 @@ SECTIONS
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
PROVIDE(__metal_boot_hart = 0);
+ PROVIDE(__metal_chicken_bit = 0);
.init :
diff --git a/bsp/coreip-e31-rtl/metal.scratchpad.lds b/bsp/coreip-e31-rtl/metal.scratchpad.lds
index d05f5c2..8cfb05e 100644
--- a/bsp/coreip-e31-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-e31-rtl/metal.scratchpad.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49 */
+/* [XXXXX] 28-05-2019 10-05-57 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -30,6 +30,7 @@ SECTIONS
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
PROVIDE(__metal_boot_hart = 0);
+ PROVIDE(__metal_chicken_bit = 0);
.init :
diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk
index afc60e3..24dc2e9 100644
--- a/bsp/coreip-e31-rtl/settings.mk
+++ b/bsp/coreip-e31-rtl/settings.mk
@@ -1,14 +1,16 @@
# Copyright 2019 SiFive, Inc #
# SPDX-License-Identifier: Apache-2.0 #
# ----------------------------------- #
-# [XXXXX] 23-05-2019 13-29-49 #
+# [XXXXX] 28-05-2019 10-05-57 #
# ----------------------------------- #
RISCV_ARCH=rv32imac
RISCV_ABI=ilp32
RISCV_CMODEL=medlow
+RISCV_SERIES=sifive-3-series
COREIP_MEM_WIDTH=32
TARGET_TAGS=rtl
TARGET_DHRY_ITERS=2000
+TARGET_CORE_ITERS=5