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authorBunnaroath Sou <35707615+bsousi5@users.noreply.github.com>2019-03-02 09:18:48 -0800
committerGitHub <noreply@github.com>2019-03-02 09:18:48 -0800
commit13bc9767e23880849142526638a7d4a1110e5a4c (patch)
tree2efee76ed7a719364fc916307aacf8a44927c005 /bsp/coreip-e31
parentfb3cddda6c0342ae6c91918e769eecafbabb55b0 (diff)
parent3cd57c399b080cc3eee813c339258fbb287bf95e (diff)
Merge pull request #186 from sifive/coreip-19.2
Update BSP for 19.2 coreip release
Diffstat (limited to 'bsp/coreip-e31')
-rw-r--r--bsp/coreip-e31/design.dts39
1 files changed, 19 insertions, 20 deletions
diff --git a/bsp/coreip-e31/design.dts b/bsp/coreip-e31/design.dts
index c589362..7c527ec 100644
--- a/bsp/coreip-e31/design.dts
+++ b/bsp/coreip-e31/design.dts
@@ -8,21 +8,21 @@
L15: cpus {
#address-cells = <1>;
#size-cells = <0>;
- L6: cpu@0 {
+ L7: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <16384>;
- reg = <0>;
+ reg = <0x0>;
riscv,isa = "rv32imac";
- sifive,dtim = <&L5>;
- sifive,itim = <&L4>;
+ sifive,dtim = <&L6>;
+ sifive,itim = <&L5>;
status = "okay";
timebase-frequency = <1000000>;
hardware-exec-breakpoint-count = <4>;
- L3: interrupt-controller {
+ L4: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
@@ -41,63 +41,62 @@
L12: ahb-periph-port@20000000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "simple-bus";
+ compatible = "sifive,ahb-periph-port", "sifive,ahb-port", "sifive,periph-port", "simple-bus";
ranges = <0x20000000 0x20000000 0x20000000>;
};
L11: ahb-sys-port@40000000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "simple-bus";
+ compatible = "sifive,ahb-sys-port", "sifive,ahb-port", "sifive,sys-port", "simple-bus";
ranges = <0x40000000 0x40000000 0x20000000>;
};
- L1: clint@2000000 {
+ L2: clint@2000000 {
compatible = "riscv,clint0";
- interrupts-extended = <&L3 3 &L3 7>;
+ interrupts-extended = <&L4 3 &L4 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
- L2: debug-controller@0 {
+ L3: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
- interrupts-extended = <&L3 65535>;
+ interrupts-extended = <&L4 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
- L5: dtim@80000000 {
+ L6: dtim@80000000 {
compatible = "sifive,dtim0";
reg = <0x80000000 0x10000>;
reg-names = "mem";
};
- L8: error-device@3000 {
+ L0: error-device@3000 {
compatible = "sifive,error0";
reg = <0x3000 0x1000>;
- reg-names = "mem";
};
L9: global-external-interrupts {
compatible = "sifive,global-external-interrupts0";
- interrupt-parent = <&L0>;
+ interrupt-parent = <&L1>;
interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>;
};
- L0: interrupt-controller@c000000 {
+ L1: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
- interrupts-extended = <&L3 11>;
+ interrupts-extended = <&L4 11>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <127>;
};
- L4: itim@8000000 {
+ L5: itim@8000000 {
compatible = "sifive,itim0";
reg = <0x8000000 0x4000>;
reg-names = "mem";
};
L10: local-external-interrupts-0 {
compatible = "sifive,local-external-interrupts0";
- interrupt-parent = <&L3>;
+ interrupt-parent = <&L4>;
interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
};
- L7: teststatus@4000 {
+ L8: teststatus@4000 {
compatible = "sifive,test0";
reg = <0x4000 0x1000>;
reg-names = "control";