Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty

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+The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications.
+
+This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports:
+        - 1 hart with RV32IMAC core
+        - 4 hardware breakpoints
+        - Physical Mempory Protectin with 8 regions
+        - 16 local interrupts signal that can be connected to off core complex devices
+        - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+~