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| author | hsiang-chia.huang <hsiangchia.huang@sifive.com> | 2019-05-24 10:22:08 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-24 10:22:08 +0800 |
| commit | faf58a49c3b6421107ada0e8af43170a5ffafcea (patch) | |
| tree | 3996d52a748ae2420b5c9c6c9efe4158d5dece53 /bsp/coreip-e34-rtl/design.dts | |
| parent | 7817c5e85cb6f9f6d5b98f6702fa4b7d1fb99e02 (diff) | |
| parent | 2c0269905929128bd0bd13a55ae3d8afd60a1af6 (diff) | |
Merge branch 'development-19.05' into dhrystone_19.05
Diffstat (limited to 'bsp/coreip-e34-rtl/design.dts')
| -rw-r--r-- | bsp/coreip-e34-rtl/design.dts | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/bsp/coreip-e34-rtl/design.dts b/bsp/coreip-e34-rtl/design.dts index 142e9d4..745f2b4 100644 --- a/bsp/coreip-e34-rtl/design.dts +++ b/bsp/coreip-e34-rtl/design.dts @@ -17,6 +17,7 @@ i-cache-size = <16384>; reg = <0x0>; riscv,isa = "rv32imafc"; + riscv,pmpregions = <8>; sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; @@ -34,10 +35,6 @@ #size-cells = <1>; compatible = "SiFive,FE340G-soc", "fe340-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L12: ahb-periph-port@20000000 { #address-cells = <1>; #size-cells = <1>; |