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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-05-23 21:11:59 +0000
committerGitHub <noreply@github.com>2019-05-23 21:11:59 +0000
commit2c0269905929128bd0bd13a55ae3d8afd60a1af6 (patch)
tree8a1e97f1d80e73284f791d11b80935bcea547a61 /bsp/coreip-e34-rtl
parente3804d42d321b5ebf3d2ef989a97c09b412393bf (diff)
parent2cc2f5e07ad2bfdefc03d443a533d1c5455c283f (diff)
Merge pull request #257 from sifive/choose-boot-hart
DeviceTree can request a specific boot hart with 'metal,boothart' property in the chosen node
Diffstat (limited to 'bsp/coreip-e34-rtl')
-rw-r--r--bsp/coreip-e34-rtl/metal-inline.h3
-rw-r--r--bsp/coreip-e34-rtl/metal-platform.h2
-rw-r--r--bsp/coreip-e34-rtl/metal.default.lds3
-rw-r--r--bsp/coreip-e34-rtl/metal.h12
-rw-r--r--bsp/coreip-e34-rtl/metal.ramrodata.lds3
-rw-r--r--bsp/coreip-e34-rtl/metal.scratchpad.lds3
-rw-r--r--bsp/coreip-e34-rtl/settings.mk3
7 files changed, 22 insertions, 7 deletions
diff --git a/bsp/coreip-e34-rtl/metal-inline.h b/bsp/coreip-e34-rtl/metal-inline.h
index 30e90fa..8a7c179 100644
--- a/bsp/coreip-e34-rtl/metal-inline.h
+++ b/bsp/coreip-e34-rtl/metal-inline.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-34 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -27,6 +27,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte
/* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu);
extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu);
diff --git a/bsp/coreip-e34-rtl/metal-platform.h b/bsp/coreip-e34-rtl/metal-platform.h
index 7abc816..4b128f9 100644
--- a/bsp/coreip-e34-rtl/metal-platform.h
+++ b/bsp/coreip-e34-rtl/metal-platform.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-34 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
#ifndef COREIP_E34_RTL__METAL_PLATFORM_H
diff --git a/bsp/coreip-e34-rtl/metal.default.lds b/bsp/coreip-e34-rtl/metal.default.lds
index f29e650..f687862 100644
--- a/bsp/coreip-e34-rtl/metal.default.lds
+++ b/bsp/coreip-e34-rtl/metal.default.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-34 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+ PROVIDE(__metal_boot_hart = 0);
.init :
diff --git a/bsp/coreip-e34-rtl/metal.h b/bsp/coreip-e34-rtl/metal.h
index 2019930..a77fc08 100644
--- a/bsp/coreip-e34-rtl/metal.h
+++ b/bsp/coreip-e34-rtl/metal.h
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-34 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
#ifndef ASSEMBLY
@@ -175,6 +175,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte
/* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu)
+{
+ if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+ return 0;
+ }
+ else {
+ return -1;
+ }
+}
+
static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
{
if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
diff --git a/bsp/coreip-e34-rtl/metal.ramrodata.lds b/bsp/coreip-e34-rtl/metal.ramrodata.lds
index fd9fded..e75a025 100644
--- a/bsp/coreip-e34-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-e34-rtl/metal.ramrodata.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-34 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+ PROVIDE(__metal_boot_hart = 0);
.init :
diff --git a/bsp/coreip-e34-rtl/metal.scratchpad.lds b/bsp/coreip-e34-rtl/metal.scratchpad.lds
index 99dfa4e..d05f5c2 100644
--- a/bsp/coreip-e34-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-e34-rtl/metal.scratchpad.lds
@@ -1,7 +1,7 @@
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
-/* [XXXXX] 21-05-2019 10-54-34 */
+/* [XXXXX] 23-05-2019 13-29-49 */
/* ----------------------------------- */
OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
PROVIDE(__stack_size = __stack_size);
__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+ PROVIDE(__metal_boot_hart = 0);
.init :
diff --git a/bsp/coreip-e34-rtl/settings.mk b/bsp/coreip-e34-rtl/settings.mk
index 942bc62..dc10ea1 100644
--- a/bsp/coreip-e34-rtl/settings.mk
+++ b/bsp/coreip-e34-rtl/settings.mk
@@ -1,7 +1,7 @@
# Copyright 2019 SiFive, Inc #
# SPDX-License-Identifier: Apache-2.0 #
# ----------------------------------- #
-# [XXXXX] 21-05-2019 10-54-34 #
+# [XXXXX] 23-05-2019 13-29-49 #
# ----------------------------------- #
RISCV_ARCH=rv32imafc
@@ -11,3 +11,4 @@ RISCV_CMODEL=medlow
COREIP_MEM_WIDTH=32
TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000