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authorScott Johnson <scottj@sifive.com>2016-12-07 18:05:38 -0800
committerGitHub <noreply@github.com>2016-12-07 18:05:38 -0800
commit7011ca48a2ef9205184a03a854ba310ebcda0e40 (patch)
tree3264e0a12875a55a1d2458bb254faabbab2cc081 /bsp/coreip-e34-rtl
parent9ad15e8896557e9526a12e868801ed5e7d320298 (diff)
parente0f235fc5344ccf79fa0e5bdd64591aef3814799 (diff)
Merge pull request #17 from sifive/enable-fpu
Enable FPU in MSTATUS CSR during init
Diffstat (limited to 'bsp/coreip-e34-rtl')
0 files changed, 0 insertions, 0 deletions