diff options
| author | Bunnaroath Sou <bsou@sifive.com> | 2019-03-01 16:04:13 -0800 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-03-01 16:04:13 -0800 |
| commit | d546fffdae400e6bf86e5f0304f412ff2ca6a641 (patch) | |
| tree | c640d81a6930eec3587ba8418d7799dc613c892a /bsp/coreip-e34/README.md | |
| parent | 43b6767541e6b20d7f7c2aef39b3a4748e53b6e4 (diff) | |
Add CoreIPs E34, S54 and update S51 for 19.2 rel
Diffstat (limited to 'bsp/coreip-e34/README.md')
| -rw-r--r-- | bsp/coreip-e34/README.md | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/bsp/coreip-e34/README.md b/bsp/coreip-e34/README.md new file mode 100644 index 0000000..1953a05 --- /dev/null +++ b/bsp/coreip-e34/README.md @@ -0,0 +1,9 @@ +The SiFive E34 Standard Core adds single-precision floating-point to the SiFive E31 Standard Core, the world’s most deployed RISC-V core. The E34 enables advanced applications which require hardware floating-point capabilities such as signal processing and motor control. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAFC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |