Delete coreip BSPs

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>

1 files changed, 0 insertions, 16 deletions

diff --git a/bsp/coreip-e76-arty/README.md b/bsp/coreip-e76-arty/README.md
deleted file mode 100644
index 3dddb18..0000000
--- a/bsp/coreip-e76-arty/README.md
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-The SiFive E76 Standard Core is a high-performance 32-bit embedded processor which is fully-compliant with the RISC-V ISA. Its advanced memory subsystem enables inclusion of tightly-integrated memory and caches.
-
-The E76 is ideal for applications which require high performance -- but have power constraints (e.g., Augmented Reality and Virtual Reality , IoT Edge Compute, Biometric Signal Processing, and Industrial Automation).
-
-This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports:
-
-- 1 hart with RV32IMAFC core
-- 4 hardware breakpoints
-- Physical Memory Protection with 8 regions
-- 16 local interrupts signal that can be connected to off core complex devices
-- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
-- GPIO memory with 16 interrupt lines
-- SPI memory with 1 interrupt line
-- Serial port with 1 interrupt line
-- 4 RGB LEDS
-- 4 Buttons and 4 Switches