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authorBunnaroath Sou <bsou@sifive.com>2019-03-06 13:23:03 -0800
committerBunnaroath Sou <bsou@sifive.com>2019-03-06 13:23:03 -0800
commit51dde8b98faf94da540624b9c7bb7fffa69daee9 (patch)
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parentf7a18d3711b3bb04b7ed8294a0e47599ac15cf45 (diff)
Add E76, S76 arty targets for all 19.2 CoreIPs release
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+The SiFive E76 Standard Core is a high-performance 32-bit embedded processor which is fully-compliant with the RISC-V ISA. Its advanced memory subsystem enables inclusion of tightly-integrated memory and caches.
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+The E76 is ideal for applications which require high performance -- but have power constraints (e.g., Augmented Reality and Virtual Reality , IoT Edge Compute, Biometric Signal Processing, and Industrial Automation).
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+This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports:
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+- 1 hart with RV32IMAFC core
+- 4 hardware breakpoints
+- Physical Memory Protection with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+- GPIO memory with 16 interrupt lines
+- SPI memory with 1 interrupt line
+- Serial port with 1 interrupt line
+- 4 RGB LEDS
+- 4 Buttons and 4 Switches