diff options
| author | Bunnaroath Sou <bsou@sifive.com> | 2019-03-18 12:58:11 -0700 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-03-18 12:58:11 -0700 |
| commit | 0fe5ca97956cc15effd0c459a81c8caacbc80ac3 (patch) | |
| tree | ad49ff7afc82f2ae691b8ebea1f8f88ae806b14c /bsp/coreip-e76-arty | |
| parent | 6695a994b01585ae3dce0e492de3c4e3feb2ae4f (diff) | |
Update Arty clock to reflects HW
Diffstat (limited to 'bsp/coreip-e76-arty')
| -rw-r--r-- | bsp/coreip-e76-arty/design.dts | 2 | ||||
| -rw-r--r-- | bsp/coreip-e76-arty/metal.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/bsp/coreip-e76-arty/design.dts b/bsp/coreip-e76-arty/design.dts index bf72b33..55edc8b 100644 --- a/bsp/coreip-e76-arty/design.dts +++ b/bsp/coreip-e76-arty/design.dts @@ -29,7 +29,7 @@ reg = <0x0>; riscv,isa = "rv32imafc"; status = "okay"; - timebase-frequency = <1000000>; + timebase-frequency = <65000000>; hardware-exec-breakpoint-count = <4>; L4: interrupt-controller { #interrupt-cells = <1>; diff --git a/bsp/coreip-e76-arty/metal.h b/bsp/coreip-e76-arty/metal.h index b35bce6..2c052e0 100644 --- a/bsp/coreip-e76-arty/metal.h +++ b/bsp/coreip-e76-arty/metal.h @@ -165,7 +165,7 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, - .timebase = 1000000UL, + .timebase = 65000000UL, .interrupt_controller = &__metal_dt_interrupt_controller.controller, }; |