diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-23 14:16:04 -0700 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-28 10:06:45 -0700 |
| commit | 12485f45ebb7f96dc60951bf4365533652ac5139 (patch) | |
| tree | b38ce688ab045a41bbdcdc90462fb4e4646a0b5d /bsp/coreip-e76-rtl | |
| parent | f7960558fd35113a89025f0971f3779d884f9a53 (diff) | |
Update BSPs
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-e76-rtl')
| -rw-r--r-- | bsp/coreip-e76-rtl/metal-inline.h | 2 | ||||
| -rw-r--r-- | bsp/coreip-e76-rtl/metal-platform.h | 2 | ||||
| -rw-r--r-- | bsp/coreip-e76-rtl/metal.default.lds | 3 | ||||
| -rw-r--r-- | bsp/coreip-e76-rtl/metal.h | 12 | ||||
| -rw-r--r-- | bsp/coreip-e76-rtl/metal.ramrodata.lds | 3 | ||||
| -rw-r--r-- | bsp/coreip-e76-rtl/metal.scratchpad.lds | 3 | ||||
| -rw-r--r-- | bsp/coreip-e76-rtl/settings.mk | 4 |
7 files changed, 17 insertions, 12 deletions
diff --git a/bsp/coreip-e76-rtl/metal-inline.h b/bsp/coreip-e76-rtl/metal-inline.h index aef66bd..179e00c 100644 --- a/bsp/coreip-e76-rtl/metal-inline.h +++ b/bsp/coreip-e76-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e76-rtl/metal-platform.h b/bsp/coreip-e76-rtl/metal-platform.h index 5513ead..04908bb 100644 --- a/bsp/coreip-e76-rtl/metal-platform.h +++ b/bsp/coreip-e76-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ #ifndef COREIP_E76_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-e76-rtl/metal.default.lds b/bsp/coreip-e76-rtl/metal.default.lds index f1317d6..1289952 100644 --- a/bsp/coreip-e76-rtl/metal.default.lds +++ b/bsp/coreip-e76-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-rtl/metal.h b/bsp/coreip-e76-rtl/metal.h index 903e53d..48f7474 100644 --- a/bsp/coreip-e76-rtl/metal.h +++ b/bsp/coreip-e76-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -69,12 +69,12 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_test0.h> struct metal_memory __metal_dt_mem_memory_80000000; diff --git a/bsp/coreip-e76-rtl/metal.ramrodata.lds b/bsp/coreip-e76-rtl/metal.ramrodata.lds index 11169de..d2f4843 100644 --- a/bsp/coreip-e76-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e76-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-rtl/metal.scratchpad.lds b/bsp/coreip-e76-rtl/metal.scratchpad.lds index f1317d6..1289952 100644 --- a/bsp/coreip-e76-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e76-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-02 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-rtl/settings.mk b/bsp/coreip-e76-rtl/settings.mk index 8f9bb0b..c48d58a 100644 --- a/bsp/coreip-e76-rtl/settings.mk +++ b/bsp/coreip-e76-rtl/settings.mk @@ -1,14 +1,16 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-02 # # ----------------------------------- # RISCV_ARCH=rv32imafc RISCV_ABI=ilp32f RISCV_CMODEL=medlow +RISCV_SERIES=sifive-7-series COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl TARGET_DHRY_ITERS=2000 +TARGET_CORE_ITERS=5 |