Merge branch 'development-19.05' into dhrystone_19.05

8 files changed, 35 insertions, 24 deletions

diff --git a/bsp/coreip-e76-rtl/design.dts b/bsp/coreip-e76-rtl/design.dts
index 40c0004..25bd59c 100644
--- a/bsp/coreip-e76-rtl/design.dts
+++ b/bsp/coreip-e76-rtl/design.dts
@@ -21,6 +21,7 @@
 			next-level-cache = <&L9>;
 			reg = <0x0>;
 			riscv,isa = "rv32imafc";
+			riscv,pmpregions = <8>;
 			status = "okay";
 			timebase-frequency = <1000000>;
                         hardware-exec-breakpoint-count = <4>;
@@ -40,10 +41,6 @@
 		#size-cells = <1>;
 		compatible = "SiFive,FE710G-soc", "fe710-soc", "sifive-soc", "simple-bus";
 		ranges;
-		pmp: pmp@0 {
-			compatible = "riscv,pmp";
-			regions = <8>;
-		};
 		L11: axi4-periph-port@20000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/bsp/coreip-e76-rtl/metal-inline.h b/bsp/coreip-e76-rtl/metal-inline.h
index fe18ce9..aef66bd 100644
--- a/bsp/coreip-e76-rtl/metal-inline.h
+++ b/bsp/coreip-e76-rtl/metal-inline.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 23-05-2019 13-29-49        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
@@ -27,8 +27,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte
 
 
 /* --------------------- cpu ------------ */
+extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu);
 extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu);
 extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu);
+extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu);
 
 
 /* --------------------- sifive_plic0 ------------ */
@@ -125,11 +127,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = {
     .init_done = 0,
 };
 
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
-    .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS,
-};
-
 /* From global_external_interrupts */
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = {
     .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable,
diff --git a/bsp/coreip-e76-rtl/metal-platform.h b/bsp/coreip-e76-rtl/metal-platform.h
index fc2e618..5513ead 100644
--- a/bsp/coreip-e76-rtl/metal-platform.h
+++ b/bsp/coreip-e76-rtl/metal-platform.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 23-05-2019 13-29-49        */
 /* ----------------------------------- */
 
 #ifndef COREIP_E76_RTL__METAL_PLATFORM_H
@@ -35,11 +35,6 @@
 #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
 #define METAL_RISCV_PLIC0_CLAIM 2097156UL
 
-/* From pmp@0 */
-#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL
-
-#define METAL_RISCV_PMP
-
 /* From global_external_interrupts */
 
 #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0
diff --git a/bsp/coreip-e76-rtl/metal.default.lds b/bsp/coreip-e76-rtl/metal.default.lds
index 84b0c14..f1317d6 100644
--- a/bsp/coreip-e76-rtl/metal.default.lds
+++ b/bsp/coreip-e76-rtl/metal.default.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 23-05-2019 13-29-49        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -27,6 +27,7 @@ SECTIONS
 	__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+	PROVIDE(__metal_boot_hart = 0);
 
 
 	.init 		:
diff --git a/bsp/coreip-e76-rtl/metal.h b/bsp/coreip-e76-rtl/metal.h
index 84e5823..903e53d 100644
--- a/bsp/coreip-e76-rtl/metal.h
+++ b/bsp/coreip-e76-rtl/metal.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 23-05-2019 13-29-49        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
@@ -89,7 +89,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 /* From interrupt_controller@c000000 */
 struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000;
 
-struct metal_pmp __metal_dt_pmp_0;
+struct metal_pmp __metal_dt_pmp;
 
 /* From global_external_interrupts */
 struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts;
@@ -165,6 +165,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte
 
 
 /* --------------------- cpu ------------ */
+static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 0;
+	}
+	else {
+		return -1;
+	}
+}
+
 static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu)
 {
 	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
@@ -185,6 +195,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s
 	}
 }
 
+static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu)
+{
+	if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) {
+		return 8;
+	}
+	else {
+		return 0;
+	}
+}
+
 
 
 /* --------------------- sifive_plic0 ------------ */
@@ -746,8 +766,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = {
 
 #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller)
 
-/* From pmp@0 */
-#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0)
+#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp)
 
 /* From global_external_interrupts */
 #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc)
diff --git a/bsp/coreip-e76-rtl/metal.ramrodata.lds b/bsp/coreip-e76-rtl/metal.ramrodata.lds
index 60429dd..11169de 100644
--- a/bsp/coreip-e76-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-e76-rtl/metal.ramrodata.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 23-05-2019 13-29-49        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -27,6 +27,7 @@ SECTIONS
 	__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+	PROVIDE(__metal_boot_hart = 0);
 
 
 	.init 		:
diff --git a/bsp/coreip-e76-rtl/metal.scratchpad.lds b/bsp/coreip-e76-rtl/metal.scratchpad.lds
index 84b0c14..f1317d6 100644
--- a/bsp/coreip-e76-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-e76-rtl/metal.scratchpad.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 20-05-2019 14-26-10        */
+/* [XXXXX] 23-05-2019 13-29-49        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -27,6 +27,7 @@ SECTIONS
 	__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
+	PROVIDE(__metal_boot_hart = 0);
 
 
 	.init 		:
diff --git a/bsp/coreip-e76-rtl/settings.mk b/bsp/coreip-e76-rtl/settings.mk
index 0ef35b7..8f9bb0b 100644
--- a/bsp/coreip-e76-rtl/settings.mk
+++ b/bsp/coreip-e76-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 22-05-2019 00-09-02        #
+# [XXXXX] 23-05-2019 13-29-49        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imafc