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| author | cgsfv <cgsfv@users.noreply.github.com> | 2019-03-19 23:31:12 +0100 |
|---|---|---|
| committer | cgsfv <cgsfv@users.noreply.github.com> | 2019-03-19 23:31:12 +0100 |
| commit | 1631c82bd9d458b532ce79e15b9c3950e6706747 (patch) | |
| tree | cb0d4e66f6c6a2ab0fc9a670c002770d09045837 /bsp/coreip-e76/design.dts | |
| parent | 1e7df67a9cf7e98bcc0750a566796b3a2a51c61f (diff) | |
Reverted to naming verilog hex files .hex
Diffstat (limited to 'bsp/coreip-e76/design.dts')
0 files changed, 0 insertions, 0 deletions