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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-01-03 21:21:06 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-03 21:21:06 +0000 |
| commit | 093255eb95393d945d4e321d1dfa614669f8834b (patch) | |
| tree | 5571f5a07467fc49ed9e5a250352e8b446d94904 /bsp/coreip-s51-arty/design.dts | |
| parent | f0e161107c5d8e3c2cfef040f7a6feffad3f9c5d (diff) | |
| parent | 6c499b707ad3864aa7f66805d6c9093813a80d3d (diff) | |
Merge pull request #128 from sifive/fix-arty-clocks
Add fixed-clocks to e31 and s51 Arty targets
Diffstat (limited to 'bsp/coreip-s51-arty/design.dts')
| -rw-r--r-- | bsp/coreip-s51-arty/design.dts | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/bsp/coreip-s51-arty/design.dts b/bsp/coreip-s51-arty/design.dts index 23362f2..c0813ca 100644 --- a/bsp/coreip-s51-arty/design.dts +++ b/bsp/coreip-s51-arty/design.dts @@ -40,6 +40,11 @@ #size-cells = <1>; compatible = "SiFive,FE510G-soc", "fe510-soc", "sifive-soc", "simple-bus"; ranges; + hfclk: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32500000>; + }; L1: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L3 3 &L3 7>; @@ -105,6 +110,7 @@ interrupts = <5>; reg = <0x20000000 0x1000>; reg-names = "control"; + clocks = <&hfclk>; }; L12: spi@20004000 { compatible = "sifive,spi0"; |