Update BSPs

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>

7 files changed, 24 insertions, 19 deletions

diff --git a/bsp/coreip-s51-arty/metal-inline.h b/bsp/coreip-s51-arty/metal-inline.h
index 3d1cc63..6af2da7 100644
--- a/bsp/coreip-s51-arty/metal-inline.h
+++ b/bsp/coreip-s51-arty/metal-inline.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-04        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
diff --git a/bsp/coreip-s51-arty/metal-platform.h b/bsp/coreip-s51-arty/metal-platform.h
index 7edd9aa..b12e171 100644
--- a/bsp/coreip-s51-arty/metal-platform.h
+++ b/bsp/coreip-s51-arty/metal-platform.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-04        */
 /* ----------------------------------- */
 
 #ifndef COREIP_S51_ARTY__METAL_PLATFORM_H
diff --git a/bsp/coreip-s51-arty/metal.default.lds b/bsp/coreip-s51-arty/metal.default.lds
index 4a9e1be..52b736e 100644
--- a/bsp/coreip-s51-arty/metal.default.lds
+++ b/bsp/coreip-s51-arty/metal.default.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-04        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -30,6 +30,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 0);
 
 
 	.init 		:
diff --git a/bsp/coreip-s51-arty/metal.h b/bsp/coreip-s51-arty/metal.h
index f5087cc..bb6c1b0 100644
--- a/bsp/coreip-s51-arty/metal.h
+++ b/bsp/coreip-s51-arty/metal.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-04        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
@@ -75,19 +75,19 @@
 
 #include <metal/drivers/fixed-clock.h>
 #include <metal/memory.h>
-#include <metal/drivers/riscv,clint0.h>
-#include <metal/drivers/riscv,cpu.h>
-#include <metal/drivers/riscv,plic0.h>
+#include <metal/drivers/riscv_clint0.h>
+#include <metal/drivers/riscv_cpu.h>
+#include <metal/drivers/riscv_plic0.h>
 #include <metal/pmp.h>
-#include <metal/drivers/sifive,local-external-interrupts0.h>
-#include <metal/drivers/sifive,global-external-interrupts0.h>
-#include <metal/drivers/sifive,gpio0.h>
-#include <metal/drivers/sifive,gpio-buttons.h>
-#include <metal/drivers/sifive,gpio-leds.h>
-#include <metal/drivers/sifive,gpio-switches.h>
-#include <metal/drivers/sifive,spi0.h>
-#include <metal/drivers/sifive,test0.h>
-#include <metal/drivers/sifive,uart0.h>
+#include <metal/drivers/sifive_local-external-interrupts0.h>
+#include <metal/drivers/sifive_global-external-interrupts0.h>
+#include <metal/drivers/sifive_gpio0.h>
+#include <metal/drivers/sifive_gpio-buttons.h>
+#include <metal/drivers/sifive_gpio-leds.h>
+#include <metal/drivers/sifive_gpio-switches.h>
+#include <metal/drivers/sifive_spi0.h>
+#include <metal/drivers/sifive_test0.h>
+#include <metal/drivers/sifive_uart0.h>
 
 /* From clock@0 */
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
diff --git a/bsp/coreip-s51-arty/metal.ramrodata.lds b/bsp/coreip-s51-arty/metal.ramrodata.lds
index a280082..4652f16 100644
--- a/bsp/coreip-s51-arty/metal.ramrodata.lds
+++ b/bsp/coreip-s51-arty/metal.ramrodata.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-04        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -30,6 +30,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 0);
 
 
 	.init 		:
diff --git a/bsp/coreip-s51-arty/metal.scratchpad.lds b/bsp/coreip-s51-arty/metal.scratchpad.lds
index 16211dc..e74a0c1 100644
--- a/bsp/coreip-s51-arty/metal.scratchpad.lds
+++ b/bsp/coreip-s51-arty/metal.scratchpad.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-04        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -30,6 +30,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 0);
 
 
 	.init 		:
diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk
index 4c84306..746be02 100644
--- a/bsp/coreip-s51-arty/settings.mk
+++ b/bsp/coreip-s51-arty/settings.mk
@@ -1,12 +1,14 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 23-05-2019 13-29-49        #
+# [XXXXX] 28-05-2019 10-06-04        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv64imac
 RISCV_ABI=lp64
 RISCV_CMODEL=medany
+RISCV_SERIES=sifive-5-series
 
 TARGET_TAGS=fpga openocd
 TARGET_DHRY_ITERS=20000000
+TARGET_CORE_ITERS=5000