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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-01-07 19:06:03 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-07 19:06:03 +0000 |
| commit | 7a965490cc35a8f9880f0a7d15a28a5dfb954bfd (patch) | |
| tree | fd8ceb059aa13860b39ec536013373339d863fba /bsp/coreip-s51-arty | |
| parent | 1a8f64bd33401e2f7b743558b3453ec30a092c9a (diff) | |
| parent | 2139efac01f4bd8826eeec3cf5a60ffaf4d5c942 (diff) | |
Merge pull request #127 from sifive/itim
Add an ITIM example
Diffstat (limited to 'bsp/coreip-s51-arty')
| -rw-r--r-- | bsp/coreip-s51-arty/mee.lds | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/bsp/coreip-s51-arty/mee.lds b/bsp/coreip-s51-arty/mee.lds index d0434f8..c081d9f 100644 --- a/bsp/coreip-s51-arty/mee.lds +++ b/bsp/coreip-s51-arty/mee.lds @@ -5,6 +5,7 @@ ENTRY(_enter) MEMORY { ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x10000 + itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000 flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x20000000 } @@ -12,7 +13,9 @@ PHDRS { flash PT_LOAD; ram_init PT_LOAD; + itim_init PT_LOAD; ram PT_NULL; + itim PT_NULL; } SECTIONS @@ -117,6 +120,30 @@ SECTIONS } >flash AT>flash :flash + .litimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_target_start = . ); + } >itim AT>flash :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>flash :itim_init + + + . = ALIGN(8); + PROVIDE( mee_segment_itim_target_end = . ); + + .lalign : { . = ALIGN(4); |