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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-01-04 17:51:13 +0000
committerGitHub <noreply@github.com>2019-01-04 17:51:13 +0000
commit80912631a4df33a2bdd592e1fc40ff73310d56b5 (patch)
tree2f6c1cacd70fab3eb070847daca52517e17985f6 /bsp/coreip-s51-arty
parent093255eb95393d945d4e321d1dfa614669f8834b (diff)
parent0d260eefcf9d14e6da017254b994959923f171c7 (diff)
Merge pull request #130 from sifive/openocd
Fix OpenOCD path in Makefile and Add Configurations for Arty Boards
Diffstat (limited to 'bsp/coreip-s51-arty')
-rw-r--r--bsp/coreip-s51-arty/openocd.cfg30
1 files changed, 30 insertions, 0 deletions
diff --git a/bsp/coreip-s51-arty/openocd.cfg b/bsp/coreip-s51-arty/openocd.cfg
new file mode 100644
index 0000000..34b9f88
--- /dev/null
+++ b/bsp/coreip-s51-arty/openocd.cfg
@@ -0,0 +1,30 @@
+adapter_khz 10000
+
+#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+interface ftdi
+ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi_vid_pid 0x15ba 0x002a
+
+ftdi_layout_init 0x0808 0x0a1b
+ftdi_layout_signal nSRST -oe 0x0200
+ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi_layout_signal LED -data 0x0800
+#
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank my_first_flash fespi 0x40000000 0 0 0 $_TARGETNAME 0x20004000
+init
+#reset
+if {[ info exists pulse_srst]} {
+ ftdi_set_signal nSRST 0
+ ftdi_set_signal nSRST z
+}
+halt
+#flash protect 0 64 last off