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authorBunnaroath Sou <bsou@sifive.com>2019-02-27 15:46:57 -0800
committerBunnaroath Sou <bsou@sifive.com>2019-02-27 15:46:57 -0800
commitcbda1f5070e04de7ed3770d5dfd2e4f9abfc84b0 (patch)
treeee323a74e2355cfedd0d528a407a6d5d252e8a7c /bsp/coreip-s51-arty
parent7570a33f98d1980b9bc9e799b0b202fde2cda1ce (diff)
Spellcheck correction readme for bsp targets for E20, E21, E31/Arty, S51/Arty
Diffstat (limited to 'bsp/coreip-s51-arty')
-rw-r--r--bsp/coreip-s51-arty/README.md6
1 files changed, 3 insertions, 3 deletions
diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md
index be9d317..0290171 100644
--- a/bsp/coreip-s51-arty/README.md
+++ b/bsp/coreip-s51-arty/README.md
@@ -1,14 +1,14 @@
The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications
-This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports:
+This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports:
- 1 hart with RV64IMAC core
- 4 hardware breakpoints
-- Physical Mempory Protectin with 8 regions
+- Physical Memory Protection with 8 regions
- 16 local interrupts signal that can be connected to off core complex devices
- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
- GPIO memory with 16 interrupt lines
-- SPI memory with 1 intterupt line
+- SPI memory with 1 interrupt line
- Serial port with 1 interrupt line
- 4 RGB LEDS
- 4 Buttons and 4 Switches