summaryrefslogtreecommitdiff
path: root/bsp/coreip-s51-arty
diff options
context:
space:
mode:
authorBunnaroath Sou <bsou@sifive.com>2019-02-25 18:57:35 -0800
committerBunnaroath Sou <bsou@sifive.com>2019-02-25 18:57:35 -0800
commite18401806b38ca0f60394780191df4b72cb2f88a (patch)
tree50c31a3efbe1f1acce3aeec706c0d8d1227c0964 /bsp/coreip-s51-arty
parentbbea559f684a5eee7df45429ed55d41330f44474 (diff)
Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty
Diffstat (limited to 'bsp/coreip-s51-arty')
-rw-r--r--bsp/coreip-s51-arty/README.md13
1 files changed, 13 insertions, 0 deletions
diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md
new file mode 100644
index 0000000..6d6c04f
--- /dev/null
+++ b/bsp/coreip-s51-arty/README.md
@@ -0,0 +1,13 @@
+The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications
+
+This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports:
+ - 1 hart with RV64IMAC core
+ - 4 hardware breakpoints
+ - Physical Mempory Protectin with 8 regions
+ - 16 local interrupts signal that can be connected to off core complex devices
+ - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+ - GPIO memory with 16 interrupt lines
+ - SPI memory with 1 intterupt line
+ - Serial port with 1 interrupt line
+ - 4 RGB LEDS
+ - 4 Buttons and 4 Switches