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| author | Bunnaroath Sou <35707615+bsousi5@users.noreply.github.com> | 2019-03-02 09:18:48 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-02 09:18:48 -0800 |
| commit | 13bc9767e23880849142526638a7d4a1110e5a4c (patch) | |
| tree | 2efee76ed7a719364fc916307aacf8a44927c005 /bsp/coreip-s51/README.md | |
| parent | fb3cddda6c0342ae6c91918e769eecafbabb55b0 (diff) | |
| parent | 3cd57c399b080cc3eee813c339258fbb287bf95e (diff) | |
Merge pull request #186 from sifive/coreip-19.2
Update BSP for 19.2 coreip release
Diffstat (limited to 'bsp/coreip-s51/README.md')
| -rw-r--r-- | bsp/coreip-s51/README.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md index 60f75bf..bf808d1 100644 --- a/bsp/coreip-s51/README.md +++ b/bsp/coreip-s51/README.md @@ -6,4 +6,4 @@ This core target is suitable with Verilog RTL for verification and running appli - 4 hardware breakpoints - Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices -- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |