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author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-07 22:47:38 +0000 |
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committer | GitHub <noreply@github.com> | 2019-03-07 22:47:38 +0000 |
commit | 2b9cbfe9011bca74aee3c1204d7db4b4236b23f0 (patch) | |
tree | fccb6fa1d7c2c065642cb21cc4d421e3ae8206eb /bsp/coreip-s51/README.md | |
parent | c6c0fbf23d1fc8aa9b99eae19b6e3741c8d51548 (diff) | |
parent | 983a630b07f08af869adc78cb37bf634389519af (diff) |
Merge pull request #197 from sifive/rename-rtl-targets
Rename coreip-X to coreip-X-rtl
Diffstat (limited to 'bsp/coreip-s51/README.md')
-rw-r--r-- | bsp/coreip-s51/README.md | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md deleted file mode 100644 index bf808d1..0000000 --- a/bsp/coreip-s51/README.md +++ /dev/null @@ -1,9 +0,0 @@ -The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications. - -This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - -- 1 hart with RV64IMAC core -- 4 hardware breakpoints -- Physical Memory Protection with 8 regions -- 16 local interrupts signal that can be connected to off core complex devices -- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |