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| author | Bunnaroath Sou <bsou@sifive.com> | 2019-02-27 15:26:41 -0800 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-02-27 15:26:41 -0800 |
| commit | 7570a33f98d1980b9bc9e799b0b202fde2cda1ce (patch) | |
| tree | 5755c5c187cced4e33f6661b46a47c3b2bb44433 /bsp/coreip-s51/README.md | |
| parent | 01767ffd966798887ea3719fd51adb8c606710e8 (diff) | |
| parent | 2ee3eec227ca11e0355358aa553b4618fff50bd9 (diff) | |
Merge branch 'e-series' of github.com:sifive/freedom-e-sdk into e-series
Diffstat (limited to 'bsp/coreip-s51/README.md')
| -rw-r--r-- | bsp/coreip-s51/README.md | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md index 3aa021f..a640a47 100644 --- a/bsp/coreip-s51/README.md +++ b/bsp/coreip-s51/README.md @@ -1,8 +1,9 @@ The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications. This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV64IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 8 regions - - 16 local interrupts signal that can be connected to off core complex devices - - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels + +- 1 hart with RV64IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |