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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-01-30 19:37:59 +0000
committerGitHub <noreply@github.com>2019-01-30 19:37:59 +0000
commit89d973abd94faf74d7486a6c5e044935f5d63e9d (patch)
treec7188e2bfad20a2750a4155ff623a16541abfb74 /bsp/coreip-s51/design.dts
parentb629a19514606cb5dd19e0cd433b60922343f6a8 (diff)
parentc615e937538d438c46efd46f9254a2a74b591205 (diff)
Merge pull request #157 from sifive/mee-pmp-no-vtable
Add PMP example
Diffstat (limited to 'bsp/coreip-s51/design.dts')
-rw-r--r--bsp/coreip-s51/design.dts4
1 files changed, 4 insertions, 0 deletions
diff --git a/bsp/coreip-s51/design.dts b/bsp/coreip-s51/design.dts
index 000ff94..a1cb9fc 100644
--- a/bsp/coreip-s51/design.dts
+++ b/bsp/coreip-s51/design.dts
@@ -33,6 +33,10 @@
#size-cells = <2>;
compatible = "SiFive,FE510G-soc", "fe510-soc", "sifive-soc", "simple-bus";
ranges;
+ pmp: pmp@0 {
+ compatible = "riscv,pmp";
+ regions = <8>;
+ };
L12: axi4-periph-port@20000000 {
#address-cells = <2>;
#size-cells = <2>;