Add corrected formatting for bullet lists

Markdown bullet lists should: (1) have a blank line before and after
the list; (2) start each list item at the beginning of the line (no leading white-space)

The markdown processor in Freedom Studio enforces these standards and does
not render correctly otherwise.

1 files changed, 6 insertions, 5 deletions

diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md
index 3aa021f..a640a47 100644
--- a/bsp/coreip-s51/README.md
+++ b/bsp/coreip-s51/README.md
@@ -1,8 +1,9 @@
 The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications.
 
 This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports:
-        - 1 hart with RV64IMAC core
-        - 4 hardware breakpoints
-        - Physical Mempory Protectin with 8 regions
-        - 16 local interrupts signal that can be connected to off core complex devices
-        - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+
+- 1 hart with RV64IMAC core
+- 4 hardware breakpoints
+- Physical Mempory Protectin with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels