diff options
| author | Bunnaroath Sou <bsou@sifive.com> | 2019-02-25 18:57:35 -0800 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-02-25 18:57:35 -0800 |
| commit | e18401806b38ca0f60394780191df4b72cb2f88a (patch) | |
| tree | 50c31a3efbe1f1acce3aeec706c0d8d1227c0964 /bsp/coreip-s51 | |
| parent | bbea559f684a5eee7df45429ed55d41330f44474 (diff) | |
Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty
Diffstat (limited to 'bsp/coreip-s51')
| -rw-r--r-- | bsp/coreip-s51/README.md | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md new file mode 100644 index 0000000..3aa021f --- /dev/null +++ b/bsp/coreip-s51/README.md @@ -0,0 +1,8 @@ +The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV64IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 8 regions + - 16 local interrupts signal that can be connected to off core complex devices + - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |