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author | Bunnaroath Sou <bsou@sifive.com> | 2019-03-18 12:58:11 -0700 |
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committer | Bunnaroath Sou <bsou@sifive.com> | 2019-03-18 12:58:11 -0700 |
commit | 0fe5ca97956cc15effd0c459a81c8caacbc80ac3 (patch) | |
tree | ad49ff7afc82f2ae691b8ebea1f8f88ae806b14c /bsp/coreip-s54-arty/design.dts | |
parent | 6695a994b01585ae3dce0e492de3c4e3feb2ae4f (diff) |
Update Arty clock to reflects HW
Diffstat (limited to 'bsp/coreip-s54-arty/design.dts')
-rw-r--r-- | bsp/coreip-s54-arty/design.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsp/coreip-s54-arty/design.dts b/bsp/coreip-s54-arty/design.dts index 7738c2a..ae42f18 100644 --- a/bsp/coreip-s54-arty/design.dts +++ b/bsp/coreip-s54-arty/design.dts @@ -28,7 +28,7 @@ sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; - timebase-frequency = <1000000>; + timebase-frequency = <65000000>; hardware-exec-breakpoint-count = <4>; L4: interrupt-controller { #interrupt-cells = <1>; |