summaryrefslogtreecommitdiff
path: root/bsp/coreip-s54-rtl/README.md
diff options
context:
space:
mode:
authorNathaniel Graff <nathaniel.graff@sifive.com>2019-03-07 22:47:38 +0000
committerGitHub <noreply@github.com>2019-03-07 22:47:38 +0000
commit2b9cbfe9011bca74aee3c1204d7db4b4236b23f0 (patch)
treefccb6fa1d7c2c065642cb21cc4d421e3ae8206eb /bsp/coreip-s54-rtl/README.md
parentc6c0fbf23d1fc8aa9b99eae19b6e3741c8d51548 (diff)
parent983a630b07f08af869adc78cb37bf634389519af (diff)
Merge pull request #197 from sifive/rename-rtl-targets
Rename coreip-X to coreip-X-rtl
Diffstat (limited to 'bsp/coreip-s54-rtl/README.md')
-rw-r--r--bsp/coreip-s54-rtl/README.md11
1 files changed, 11 insertions, 0 deletions
diff --git a/bsp/coreip-s54-rtl/README.md b/bsp/coreip-s54-rtl/README.md
new file mode 100644
index 0000000..e04dcf5
--- /dev/null
+++ b/bsp/coreip-s54-rtl/README.md
@@ -0,0 +1,11 @@
+The SiFive S54 Standard Core is a 64-bit embedded processor that is fully-compliant with the RISC-V ISA. It adds support for the F and D standard extensions, which provide the S54 with double-precision floating-point capabilities.
+
+The S54 is ideal for demanding applications such as avionics, signal processing, and industrial automation.
+
+This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports:
+
+- 1 hart with RV64IMAFDC core
+- 4 hardware breakpoints
+- Physical Memory Protection with 8 regions
+- 16 local interrupts signal that can be connected to off core complex devices
+- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels