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author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-07 11:28:06 -0800 |
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committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-07 14:45:59 -0800 |
commit | 983a630b07f08af869adc78cb37bf634389519af (patch) | |
tree | fccb6fa1d7c2c065642cb21cc4d421e3ae8206eb /bsp/coreip-s54/README.md | |
parent | c6c0fbf23d1fc8aa9b99eae19b6e3741c8d51548 (diff) |
Rename coreip-X to coreip-X-rtl
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-s54/README.md')
-rw-r--r-- | bsp/coreip-s54/README.md | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/bsp/coreip-s54/README.md b/bsp/coreip-s54/README.md deleted file mode 100644 index e04dcf5..0000000 --- a/bsp/coreip-s54/README.md +++ /dev/null @@ -1,11 +0,0 @@ -The SiFive S54 Standard Core is a 64-bit embedded processor that is fully-compliant with the RISC-V ISA. It adds support for the F and D standard extensions, which provide the S54 with double-precision floating-point capabilities. - -The S54 is ideal for demanding applications such as avionics, signal processing, and industrial automation. - -This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - -- 1 hart with RV64IMAFDC core -- 4 hardware breakpoints -- Physical Memory Protection with 8 regions -- 16 local interrupts signal that can be connected to off core complex devices -- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |