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authorBunnaroath Sou <bsou@sifive.com>2019-03-01 19:09:27 -0800
committerBunnaroath Sou <bsou@sifive.com>2019-03-01 19:09:27 -0800
commite7a3c3a2999a7b1ffbab96b5bc83061ca6f387d3 (patch)
treed087b43efce3f2fd2483a86743d081bca3c8371d /bsp/coreip-s54
parentd546fffdae400e6bf86e5f0304f412ff2ca6a641 (diff)
Add CoreIPs E76, S76 for 19.2 rel
Diffstat (limited to 'bsp/coreip-s54')
-rw-r--r--bsp/coreip-s54/README.md2
-rw-r--r--bsp/coreip-s54/settings.mk2
2 files changed, 2 insertions, 2 deletions
diff --git a/bsp/coreip-s54/README.md b/bsp/coreip-s54/README.md
index 07b7159..e04dcf5 100644
--- a/bsp/coreip-s54/README.md
+++ b/bsp/coreip-s54/README.md
@@ -8,4 +8,4 @@ This core target is suitable with Verilog RTL for verification and running appli
- 4 hardware breakpoints
- Physical Memory Protection with 8 regions
- 16 local interrupts signal that can be connected to off core complex devices
-- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
+- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
diff --git a/bsp/coreip-s54/settings.mk b/bsp/coreip-s54/settings.mk
index 1cc5d31..3d1ed75 100644
--- a/bsp/coreip-s54/settings.mk
+++ b/bsp/coreip-s54/settings.mk
@@ -1,3 +1,3 @@
RISCV_ARCH=rv64imafdc
RISCV_ABI=lp64d
-COREIP_MEM_WIDTH=32
+COREIP_MEM_WIDTH=64