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author | Bunnaroath Sou <bsou@sifive.com> | 2019-03-06 13:23:03 -0800 |
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committer | Bunnaroath Sou <bsou@sifive.com> | 2019-03-06 13:23:03 -0800 |
commit | 51dde8b98faf94da540624b9c7bb7fffa69daee9 (patch) | |
tree | 77bee6f7125d331a7353f9df6a43a3d20747f3f0 /bsp/coreip-s76-arty/README.md | |
parent | f7a18d3711b3bb04b7ed8294a0e47599ac15cf45 (diff) |
Add E76, S76 arty targets for all 19.2 CoreIPs release
Diffstat (limited to 'bsp/coreip-s76-arty/README.md')
-rw-r--r-- | bsp/coreip-s76-arty/README.md | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/bsp/coreip-s76-arty/README.md b/bsp/coreip-s76-arty/README.md new file mode 100644 index 0000000..67be221 --- /dev/null +++ b/bsp/coreip-s76-arty/README.md @@ -0,0 +1,16 @@ +The SiFive S76 Standard Core is a high-performance 64-bit embedded processor which is fully-compliant with the RISC-V ISA. + +The S76 is ideal for latency-sensitive applications in domains such as storage and networking that require 64-bit memory addressability (e.g. In-storage Compute, Edge Compute, 5G Modems, Object storage etc.) + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV64IMAFDC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches |