diff options
| author | Bunnaroath Sou <bsou@sifive.com> | 2019-03-18 12:58:11 -0700 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-03-18 12:58:11 -0700 |
| commit | 0fe5ca97956cc15effd0c459a81c8caacbc80ac3 (patch) | |
| tree | ad49ff7afc82f2ae691b8ebea1f8f88ae806b14c /bsp/coreip-s76-arty/design.dts | |
| parent | 6695a994b01585ae3dce0e492de3c4e3feb2ae4f (diff) | |
Update Arty clock to reflects HW
Diffstat (limited to 'bsp/coreip-s76-arty/design.dts')
| -rw-r--r-- | bsp/coreip-s76-arty/design.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsp/coreip-s76-arty/design.dts b/bsp/coreip-s76-arty/design.dts index f43d9c5..736d909 100644 --- a/bsp/coreip-s76-arty/design.dts +++ b/bsp/coreip-s76-arty/design.dts @@ -29,7 +29,7 @@ reg = <0x0>; riscv,isa = "rv64imafdc"; status = "okay"; - timebase-frequency = <1000000>; + timebase-frequency = <65000000>; hardware-exec-breakpoint-count = <4>; L4: interrupt-controller { #interrupt-cells = <1>; |