diff options
author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-28 17:10:05 +0000 |
---|---|---|
committer | GitHub <noreply@github.com> | 2019-05-28 17:10:05 +0000 |
commit | 4aa97062fb30b239e97ba6b50f35cf8e8d251469 (patch) | |
tree | b38ce688ab045a41bbdcdc90462fb4e4646a0b5d /bsp/coreip-s76-arty | |
parent | 869ef0c1a2282f52500c4004224c9c9b196626b9 (diff) | |
parent | 12485f45ebb7f96dc60951bf4365533652ac5139 (diff) |
Merge pull request #258 from sifive/remove-commas
Remove commas from Freedom Metal filenames
Diffstat (limited to 'bsp/coreip-s76-arty')
-rw-r--r-- | bsp/coreip-s76-arty/metal-inline.h | 2 | ||||
-rw-r--r-- | bsp/coreip-s76-arty/metal-platform.h | 2 | ||||
-rw-r--r-- | bsp/coreip-s76-arty/metal.default.lds | 3 | ||||
-rw-r--r-- | bsp/coreip-s76-arty/metal.h | 24 | ||||
-rw-r--r-- | bsp/coreip-s76-arty/metal.ramrodata.lds | 3 | ||||
-rw-r--r-- | bsp/coreip-s76-arty/metal.scratchpad.lds | 3 | ||||
-rw-r--r-- | bsp/coreip-s76-arty/settings.mk | 4 |
7 files changed, 23 insertions, 18 deletions
diff --git a/bsp/coreip-s76-arty/metal-inline.h b/bsp/coreip-s76-arty/metal-inline.h index 56168da..204a35b 100644 --- a/bsp/coreip-s76-arty/metal-inline.h +++ b/bsp/coreip-s76-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-s76-arty/metal-platform.h b/bsp/coreip-s76-arty/metal-platform.h index c849584..c52e5ac 100644 --- a/bsp/coreip-s76-arty/metal-platform.h +++ b/bsp/coreip-s76-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ #ifndef COREIP_S76_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-s76-arty/metal.default.lds b/bsp/coreip-s76-arty/metal.default.lds index fc983a7..d22d88e 100644 --- a/bsp/coreip-s76-arty/metal.default.lds +++ b/bsp/coreip-s76-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-s76-arty/metal.h b/bsp/coreip-s76-arty/metal.h index 87f6ae5..0a6efa6 100644 --- a/bsp/coreip-s76-arty/metal.h +++ b/bsp/coreip-s76-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -75,18 +75,18 @@ #include <metal/drivers/fixed-clock.h> #include <metal/memory.h> -#include <metal/drivers/riscv,clint0.h> -#include <metal/drivers/riscv,cpu.h> -#include <metal/drivers/riscv,plic0.h> +#include <metal/drivers/riscv_clint0.h> +#include <metal/drivers/riscv_cpu.h> +#include <metal/drivers/riscv_plic0.h> #include <metal/pmp.h> -#include <metal/drivers/sifive,global-external-interrupts0.h> -#include <metal/drivers/sifive,gpio0.h> -#include <metal/drivers/sifive,gpio-buttons.h> -#include <metal/drivers/sifive,gpio-leds.h> -#include <metal/drivers/sifive,gpio-switches.h> -#include <metal/drivers/sifive,spi0.h> -#include <metal/drivers/sifive,test0.h> -#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive_global-external-interrupts0.h> +#include <metal/drivers/sifive_gpio0.h> +#include <metal/drivers/sifive_gpio-buttons.h> +#include <metal/drivers/sifive_gpio-leds.h> +#include <metal/drivers/sifive_gpio-switches.h> +#include <metal/drivers/sifive_spi0.h> +#include <metal/drivers/sifive_test0.h> +#include <metal/drivers/sifive_uart0.h> /* From tlclk */ struct __metal_driver_fixed_clock __metal_dt_tlclk; diff --git a/bsp/coreip-s76-arty/metal.ramrodata.lds b/bsp/coreip-s76-arty/metal.ramrodata.lds index f53fd33..8b20b53 100644 --- a/bsp/coreip-s76-arty/metal.ramrodata.lds +++ b/bsp/coreip-s76-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-s76-arty/metal.scratchpad.lds b/bsp/coreip-s76-arty/metal.scratchpad.lds index eadc43f..05c0700 100644 --- a/bsp/coreip-s76-arty/metal.scratchpad.lds +++ b/bsp/coreip-s76-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-10 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-s76-arty/settings.mk b/bsp/coreip-s76-arty/settings.mk index ded9d2f..6928c1e 100644 --- a/bsp/coreip-s76-arty/settings.mk +++ b/bsp/coreip-s76-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-10 # # ----------------------------------- # RISCV_ARCH=rv64imafdc RISCV_ABI=lp64d RISCV_CMODEL=medany +RISCV_SERIES=sifive-7-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 |