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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-06-19 15:26:20 -0700 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-06-19 15:27:52 -0700 |
| commit | 0d6aad1a8c3b806716add4b5bb6954984d508ab3 (patch) | |
| tree | 9c6ef58cd92036a9c9eb23713e8f646af43e456e /bsp/coreip-s76-rtl/README.md | |
| parent | 00a58b4a52a6a3678c1359d76a8647fd5f528b9b (diff) | |
Delete coreip BSPs
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-s76-rtl/README.md')
| -rw-r--r-- | bsp/coreip-s76-rtl/README.md | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/bsp/coreip-s76-rtl/README.md b/bsp/coreip-s76-rtl/README.md deleted file mode 100644 index 9623a83..0000000 --- a/bsp/coreip-s76-rtl/README.md +++ /dev/null @@ -1,11 +0,0 @@ -The SiFive S76 Standard Core is a high-performance 64-bit embedded processor which is fully-compliant with the RISC-V ISA. - -The S76 is ideal for latency-sensitive applications in domains such as storage and networking that require 64-bit memory addressability (e.g. In-storage Compute, Edge Compute, 5G Modems, Object storage etc.) - -This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - -- 1 hart with RV64IMAFDC core -- 4 hardware breakpoints -- Physical Memory Protection with 8 regions -- 16 local interrupts signal that can be connected to off core complex devices -- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |