diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-06-21 16:36:57 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-21 16:36:57 +0000 |
| commit | 0f5761d7d32edddf93f302f52b903e8acca08c5e (patch) | |
| tree | 46ff4106f51fb6d5f682cf6af73ef1a4ab5f147e /bsp/coreip-s76-rtl/README.md | |
| parent | eecf71d7cf0ec12997dbceffde190b1086595908 (diff) | |
| parent | 713237cb963ebf81aca0715d8a770fdbe5d71cb9 (diff) | |
Merge pull request #287 from sifive/remove-coreip-bsps
Remove all CoreIP BSPs
Diffstat (limited to 'bsp/coreip-s76-rtl/README.md')
| -rw-r--r-- | bsp/coreip-s76-rtl/README.md | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/bsp/coreip-s76-rtl/README.md b/bsp/coreip-s76-rtl/README.md deleted file mode 100644 index 9623a83..0000000 --- a/bsp/coreip-s76-rtl/README.md +++ /dev/null @@ -1,11 +0,0 @@ -The SiFive S76 Standard Core is a high-performance 64-bit embedded processor which is fully-compliant with the RISC-V ISA. - -The S76 is ideal for latency-sensitive applications in domains such as storage and networking that require 64-bit memory addressability (e.g. In-storage Compute, Edge Compute, 5G Modems, Object storage etc.) - -This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - -- 1 hart with RV64IMAFDC core -- 4 hardware breakpoints -- Physical Memory Protection with 8 regions -- 16 local interrupts signal that can be connected to off core complex devices -- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |