diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-07 11:28:06 -0800 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-07 14:45:59 -0800 |
| commit | 983a630b07f08af869adc78cb37bf634389519af (patch) | |
| tree | fccb6fa1d7c2c065642cb21cc4d421e3ae8206eb /bsp/coreip-s76-rtl/README.md | |
| parent | c6c0fbf23d1fc8aa9b99eae19b6e3741c8d51548 (diff) | |
Rename coreip-X to coreip-X-rtl
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-s76-rtl/README.md')
| -rw-r--r-- | bsp/coreip-s76-rtl/README.md | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/bsp/coreip-s76-rtl/README.md b/bsp/coreip-s76-rtl/README.md new file mode 100644 index 0000000..9623a83 --- /dev/null +++ b/bsp/coreip-s76-rtl/README.md @@ -0,0 +1,11 @@ +The SiFive S76 Standard Core is a high-performance 64-bit embedded processor which is fully-compliant with the RISC-V ISA. + +The S76 is ideal for latency-sensitive applications in domains such as storage and networking that require 64-bit memory addressability (e.g. In-storage Compute, Edge Compute, 5G Modems, Object storage etc.) + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV64IMAFDC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |