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| author | Bunnaroath Sou <35707615+bsousi5@users.noreply.github.com> | 2019-03-19 18:16:56 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-19 18:16:56 -0700 |
| commit | 318ac16f2b0fdab7ac82758993e7e6835b94115d (patch) | |
| tree | bd15b52cccb8ff4f9c6e184db10aa8d4520b7aa0 /bsp/coreip-s76-rtl | |
| parent | 0f8c780d82b2ec3eda351229e79953bbde7bb95a (diff) | |
| parent | ac5e78c355567d2ed430e22b4c1d119188904d83 (diff) | |
Merge pull request #209 from sifive/arty-19.2
Make rtl target to use ram from dtim, flash from testram
Diffstat (limited to 'bsp/coreip-s76-rtl')
0 files changed, 0 insertions, 0 deletions