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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-04-11 21:40:27 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-11 21:40:27 +0000 |
| commit | b47459592db6ee7aef2a86b2010d05b8ced7eba9 (patch) | |
| tree | d1c07a9437495210ae266766f6988c0e0bceba17 /bsp/coreip-s76-rtl | |
| parent | a4d97b7aec6eb939eb1f61883591ba5cc58be258 (diff) | |
| parent | 45a50ed76caa304ba112a312d8309a625be64b7a (diff) | |
Merge pull request #233 from sifive/7-series-pmp
Add PMP nodes to all targets except e20
Diffstat (limited to 'bsp/coreip-s76-rtl')
| -rw-r--r-- | bsp/coreip-s76-rtl/design.dts | 4 | ||||
| -rw-r--r-- | bsp/coreip-s76-rtl/metal.h | 11 |
2 files changed, 15 insertions, 0 deletions
diff --git a/bsp/coreip-s76-rtl/design.dts b/bsp/coreip-s76-rtl/design.dts index f27053d..a4fd9c8 100644 --- a/bsp/coreip-s76-rtl/design.dts +++ b/bsp/coreip-s76-rtl/design.dts @@ -40,6 +40,10 @@ #size-cells = <2>; compatible = "SiFive,FS760G-soc", "fs710-soc", "sifive-soc", "simple-bus"; ranges; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; L11: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; diff --git a/bsp/coreip-s76-rtl/metal.h b/bsp/coreip-s76-rtl/metal.h index 8b8acbc..8f096d0 100644 --- a/bsp/coreip-s76-rtl/metal.h +++ b/bsp/coreip-s76-rtl/metal.h @@ -64,6 +64,9 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; asm (".weak __metal_dt_interrupt_controller_c000000"); struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; +asm (".weak __metal_dt_pmp_0"); +struct metal_pmp __metal_dt_pmp_0; + /* From global_external_interrupts */ asm (".weak __metal_dt_global_external_interrupts"); struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -117,6 +120,11 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .interrupt_controller = 1, }; +/* From pmp@0 */ +struct metal_pmp __metal_dt_pmp_0 = { + .num_regions = 8UL, +}; + /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0, @@ -289,6 +297,9 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) +/* From pmp@0 */ +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) + /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) |